The present invention relates to a frequency divider circuit.
Frequency divider circuits are used in numerous devices such as, for example, counting circuits, phase loops, frequency synthesizers or, again, information encryption circuits.
The invention shall be described more particularly with reference to the making of counting circuits but relates more generally to every field in which frequency dividers play a role.
There are two types of counting circuits. There are asynchronous counters and synchronous counters. The invention relates more particularly to synchronous counters but may also relate to asynchronous counters.
N-bit synchronous counters can generate 2.sup.N different combinations.
Their resetting is done automatically when there is an overflow of capacity, i.e. at the 2.sup.Nth clock stroke. It is then said that the frequency is divided by 2.sup.N.
It is often necessary to carry out a division by any number n before reaching the 2.sup.Nth clock stroke. According to the prior art, the counting circuit then comprises additional logic functions that can be used to carry out a resetting operation at the desired point in time. Each code generated by the counter is compared with one and the same logic word. The comparison between the codes and the logic word gives a signal that permits the frequency division to the desired nth order. The comparison between the codes and the logic word necessitates the presence of a multiplexing circuit that very quickly becomes complex, once the number of bits N increases. This multiplexing circuit then takes up a great deal of space.
One drawback of the device according to the prior art is the fact that it requires a bulky circuit, the management which is all the more complicated to manage as frequent changes have to be made in the value of n. This entails heavy penalties, for example in the case of phase loops where it is necessary, very frequently, to divide a reference frequency by a variable number n.
The present invention does not have this drawback.